The present invention relates to flash memory devices and, more particularly, to NOR flash memory devices and related methods for erasing such devices.
Semiconductor memory devices are configured to retain previously stored data in the absence of power. Semiconductor memory devices may be categorized as random access memory (RAM) devices and read only memory (ROM) devices. A RAM device can be called a volatile memory because it loses stored data upon power-off. RAM devices can include dynamic RAM, static RAM, and the like. A ROM can be called a non-volatile memory because it can retain stored data upon power-off. ROM devices can include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory, and the like.
Flash memories can be classified into NAND flash memory type devices and NOR flash memory type devices. A NAND flash memory can have a string structure in which a plurality of memory cells are connected in series to a bit line, while a NOR flash memory can have a structure in which a plurality of memory cells are connected in parallel to a bit line.
FIG. 1 is a cross-sectional view of a NOR flash memory cell. Referring to FIG. 1, a memory cell 10 has a source 1, a drain 2, a first insulating film 5, a floating gate 6, a second insulating film 7, and a control gate 8. The source 1 and the drain 2 are formed on a p-type substrate 3 so as to be spaced apart from each other.
The source 1 is connected to a source line SL, and the drain 2 is connected to a bit line BL. The floating gate 6 is formed on a channel region with the first insulating film 5 below 100 Angstroms interposed therebetween. The control gate 8 is formed on the floating gate 6 with the second insulating film 7 (referred to as an ONO film) interposed therebetween. The control gate 8 is connected to a word line WL. The substrate 3 is supplied with a bulk voltage BK. The source 1, the drain 2, the control gate 8 and the substrate 3 may be supplied with given bias voltages based on selected program, erase and read operations.
A NOR flash memory includes a cell array region in which memory cells in FIG. 1 are regularly arranged in two dimensions. The patterns in the cell array region may be formed using a photolithography process, which may result in memory cells along edges of the cell array region being deformed due to their proximity to the edges. Such deformed cells may give rise to non-uniform characteristics of all memory cells in the cell array region.
In an attempt to avoid the effects of memory cells proximate to cell array region edges, a dummy cell array region may be provided in a NOR flash memory so as to surround the cell array region. For purposes of description herein, the cell array region is referred to as a “main cell array region” to differentiate the dummy cell array region.
FIG. 2 is a cross-sectional view showing a part of a cell array region of a conventional NOR flash memory, and corresponds to FIG. 2 in U.S patent publication No. 2005-0041477. In FIG. 2, the cell array regions include a main cell array region and a dummy cell array region.
During an erase operation of the NOR flash memory in FIG. 2, a first erase voltage Ve1 (e.g., −10V) is applied to a main word line WL, and a second erase voltage Ve2 (e.g., +10V), which is higher than the first erase voltage Ve1, is applied to a p-well region 3 and a dummy word line WL′. In this case, main cells are insufficiently erased due to parasitic capacitance CFG between a main floating gate FG of a first main gate pattern G1 and a dummy floating gate FG′ of a second dummy gate pattern G2′.
FIG. 3 is a cross-sectional view showing a part of another cell array region of the conventional NOR flash memory illustrated in FIG. 2. The cross-sectional view in FIG. 3 corresponds to FIG. 3 in U.S patent publication No. 2005-0041477. In FIG. 3, a symbol “Main” indicates a main cell array region, and symbols “Dummy1” and “Dummy2” indicate a first dummy cell array region and a second dummy cell array region, respectively.
During an erase operation of the NOR flash memory in FIG. 3, a first erase voltage Ve1 (e.g., −10V) is applied to a main word line MWL, a second erase voltage Ve2 (e.g. +10V), which is higher than the first erase voltage Ve1, is applied to a p-well region 53, and a third erase voltage Ve3 is applied to a dummy word line DWL. The third erase voltage Ve3 may be equal to the first erase voltage Ve1. Alternatively, the third erase voltage Ve3 may be higher than the first erase voltage Ve1 or may be lower than the second erase voltage Ve2.
With the cell array structure of the NOR flash memory in FIG. 3, during the erase operation, main cells MC2 to MCn-1 are normally erased through a well-known F-N tunneling scheme. Main cells MC1 and MCn may have an improved erase characteristic over the erase characteristic of the cell array region in FIG. 2. The improved erase characteristic may be associated with the third erase voltage Ve3 being lower than the second erase voltage Ve2. For example, because the first to fourth dummy word lines DWL1 to DWL4 are supplied with the third erase voltage Ve3 being equal to the first erase voltage Ve1 or lower than the second erase voltage Ve2, it may be possible to reduce the effects parasitic capacitance CFG described with regard to FIG. 2.
However, during fabrication processes to form the cell array structure of the NOR flash memory in FIG. 3, a coupling phenomenon may occur between word lines and/or a short-circuit phenomenon may occur through and/or circumventing one or more of the insulating films of each cell.
For example, assume that the third erase voltage Ve3 is equal to the first erase voltage Ve1, e.g., Ve3=Ve1=−10V. If a short-circuit phenomenon occurs between a substrate and an insulating film in each of outermost dummy gate patterns DG1 and DG4, during an erase operation, the p-well region 53 can be biased with a voltage lower than the second erase voltage Ve2 and the main word line MWL can be biased with a voltage higher than the first erase voltage Ve1, in which may result in the cells of the main cell array region not being sufficiently erased.